This invention relates to a semiconductor memory device and, more particularly, to an electrically programmable non-volatile semiconductor memory device and a write/read controlling method for the semiconductor memory device.
A semiconductor memory device, in which bit lines of a memory cell array are formed by impurity electrically conductive areas provided on a substrate surface, lends itself to increasing the memory capacity, because there is no isolation area between neighboring transistors separating the memory cells and hence the memory cell can be reduced in size. However, such semiconductor memory device is not up to high-speed operations, due to bit-line resistance or stray capacitance, because the bit lines are formed by impurity doped electrically conductive areas provided on a silicon substrate. The bit line length is increased due to increased storage capacity to render the high speed operation difficult. Moreover, since the bit line length is increased, the write voltage applied to a memory cell tends to be lowered due to bit line resistance.
In JP Patent Kokai Publication JP-A-6-283689, for example, there is disclosed a mask ROM configuration in which the resistance of a bit line formed by an electrically conductive region is lowered to provide for a high-speed operation. FIG. 16 shows a plan view of a memory cell of a semiconductor memory device. FIG. 17 shows its circuit configuration. On a major surface of a p-type silicon substrate 10, a plural number of n-type electrically conductive regions (N+ diffusion layers) 11, operating as source or drain of the memory cell transistor, are arranged parallel to one another at a preset interval in-between. The electrically conductive regions 11 are arranged for traversing the memory cell region and are in the form of a letter U with the web of the letter U being connected with an n-type connecting electrically conductive region 12 for a length equal to two columns. On the outer side of each conducting electrically conductive region 12 is arranged an isolated n-type auxiliary electrically conductive region 13 at a preset distance from each connecting electrically conductive region 12. On the silicon substrate 10, carrying these electrically conductive region 11, 12 and 13, a plural number of gate electrodes 15 of polycrystalline silicon are arrayed parallel to one another, with the interposition of gate insulating films, for intersecting the electrically conductive regions 11. The gate electrodes operate as word lines, such that a preset voltage is selectively applied to a row specified by row address data. On both sides of these gate electrodes 15 are arrayed selecting gate electrodes 16, similarly of polycrystalline silicon, so as to be astride the conducting electrically conductive regions 12 and the auxiliary electrically conductive regions 13. This forms a selecting transistor T2 having the selecting gate electrode 16, connecting electrically conductive regions 12 and the auxiliary electrically conductive regions 13 as its gate, source and drain, respectively. Since this selecting transistor T2 is provided every four columns on one side of the electrically conductive region 11, the gate width can be set to a broader value, depending on the size of the auxiliary electrically conductive regions 13, such that the resistance can be set to a sufficiently small value.
Since the neighboring ones of these selecting transistors T2 are driven with the common gate electrode, a P-type impurity region 19 is formed between the neighboring selecting transistors T2 to prevent current conduction across the neighboring selecting transistors T2. This device-to-isolation is achieved by for example ion implantation.
In the transistor T1, forming each memory cell, the gate electrodes, consecutive from row to row, each form a word line WL. The gate electrodes are selectively activated by selection signals derived from row address data. Similarly, in the selection transistor T2, the selecting gate electrodes 16 are common on both sides of the gate electrodes 15 such that the selecting gate electrodes 16 each form a selecting control line SL. An aluminum line 18 forms a main bit line BI, and is selectively activated on receipt of a selection signal derived from column address data. That is, when two of the aluminum lines 18 are specified in dependence upon address data, and the source voltage and the grounding voltage are applied to the so specified aluminum lines, while the selection transistor T2 connecting to the specified aluminum lines 18 is turned on in order to connect its electrically conductive region 11 to the aluminum lines 18, the two neighboring columns of the electrically conductive regions 11 are selectively activated. With the two aluminum lines, the voltage applied in the selected state is not fixed to one of the source voltage or to the ground voltage, such that the source voltage is switched to the ground voltage or vice versa depending on the combination of the selected bit lines BL.
In selecting the bit lines BL, either a neighboring pair of the bit lines or a pair of a bit line and a bit line next to the next bit line is selected. Thus, one of the transistors T1 arranged in a matrix configuration is specified in dependence upon address data and potential variations in the electrically conductive region 11 due to on/off of the MOS transistor T1 are checked by a sense amplifier, not shown, selectively connected to the aluminum line (main bit line).
Meanwhile, the memory cell of the semiconductor memory device, shown in FIGS. 16 and 17, is read-only, such that it does not allow for writing. In a configuration which allows for writing, as in an EEPROM (Electrically Erasable and Programmable Read-Only Memory), a high voltage is applied to the source or to the drain of the memory cell transistor. If the transistor is of the high voltage withstand type to diminish the on-resistance and to suppress the lowering of the current at the time of writing, the junction withstand voltage characteristics are lowered in an impurity layer serving for device isolation across the selecting transistors, thus causing breakdown of the selecting transistor.
In JP Patent Kokai Publication No. JP-A-8-32035, for example, there is disclosed a semiconductor device having two layer gate structure type memory cells, in which a diffusion layer forming local data lines (LDL0 and LDL1) of the memory cell are shared by memory cell MCs provided on a identical column and a diffusion layer forming a local source line (LSL0) is shared by memory cell MCs provided on neighboring two columns, and in which there are provided sub data lines (SDL0 and SDL1) and sub source line (SSL0), which are made up of metal wiring layer having a small sheet resistance, and being arranged in parallel corresponding to the diffusion layers composing common drain and source for coupling between the associated diffusion layer by preset number of contacts (CB and CC).
Accordingly it is an object of the present invention to provide a programmable semiconductor memory device, employing an electrically conductive layer as an impurity layer, in which the resistance value of the electrically conductive layer by the impurity layer may be diminished and in which the selecting transistors may be of the high voltage withstand type.
It is another object of the present invention to provide a semiconductor memory device in which the voltage may be prevented from being lowered at the time of writing in a memory cell and in which the memory cell readout current may be prevented from being decreased, and a method for writing and readout for the semiconductor memory device. It is yet another object of the present invention to provide a semiconductor memory device in which the sum of the resistance values of the electrically conductive layers by an impurity layer connecting to a memory cell may be kept constant without dependency on the arrangement of the memory cells in the memory cell array.
The above and other objects are attained by a semiconductor memory device, according to one aspect of the present invention, providing means for accomplishing at least one of the above objects, comprises a plurality of electrically conductive regions extending parallel to one another on a substrate surface forming a memory cell array area, wherein the electrically conductive regions are connected two by two by wiring to form a plurality of sets of sub bit lines, each set of the sub bit lines being connected to a main bit line via a selection transistor, a plurality of the selection transistors are arranged on both ends of the memory cell array in a facing relation to one another, and wherein a plural number of sets of the sub bit lines respectively connected to plural selection transistors on one end of the memory cell array and a plural number of sets of the sub bit lines respectively connected to plural selection transistors on the opposite end of the memory cell array are arranged in an interchanged fashion relative to one another.
According to the present invention, there are arranged, in a region in the memory cell array area defined between the sub bit lines of the set of sub bit lines, each one of two sets of sub bit lines respectively connected via selection transistors to two neighboring main bit lines on both sides of a main bit line to which is connected the set of sub bit lines, and each one of two sets of sub bit lines respectively connected to the two neighboring main bit lines via selection transistors on the opposite side of the memory cell array, totaling at four sub bit lines.
According to the present invention, isolation between the selection transistors is by a field oxide film.
Of respective longitudinal ends of the paired electrically conductive regions of the set of sub bit lines, the respective ends lying on the side of the selection transistor associated with the set of the sub bit lines lying on the side of the selection transistor associated with the set of sub bit lines (referred to as one side ends) are interconnected via a wiring of an upper substrate layer.
According to the present invention, one side ends of the paired electrically conductive regions forming the set of sub bit lines, lying on the side of the selection transistors associated with the set of the sub bit lines, are interconnected by a wiring forming an upper substrate layer, while the side ends of the paired electrically conductive regions longitudinally opposite to the aforementioned on side ends are interconnected by a wiring forming an upper substrate layer.
According to the present invention, one side ends lying on the side of the selection transistors associated with the set of the sub bit lines, of one or both of the paired electrically conductive regions forming the set of sub bit lines, interconnected by the wiring, are connected to the longitudinally opposite ends thereof by an upper substrate layer.
According to the present invention, the paired electrically conductive regions forming the set of sub bit lines, interconnected by the wiring, are divided into plural stages from one longitudinal end of the memory cell array to the opposite side thereof, while thee is provided a wiring formed on an upper layer on the substrate in association with the set of the sub bit lines, so as to straddle the plural stages of the paired electrically conductive regions from the one ends connected to the selection transistors to the opposite sides. The wiring extending astride the plural stages of the paired electrically conductive regions is connected to the wiring interconnecting the paired electrically conductive regions of the respective stages.
Of respective longitudinal ends of the paired electrically conductive regions of the set of sub bit lines, the ends lying on the side of the selection transistor associated with the set of sub bit lines (referred to as one side ends) are interconnected via a first wiring of an upper substrate layer, and wherein the ends longitudinally opposite to the one lateral side end, are interconnected by a second wiring on an upper layer on the substrate, while the first wiring and the second wiring are interconnected via a third wiring on an upper layer on the substrate.
Of respective longitudinal ends of the paired electrically conductive regions of the set of sub bit lines, the ends lying on the side of the selection transistor associated with the set of sub bit lines (referred to as one side ends) are interconnected via a first wiring of an upper substrate layer, and wherein the ends longitudinally opposite to the one lateral side end, are interconnected by a second wiring on an upper layer on the substrate, both longitudinal ends of the electrically conductive regions being interconnected via a third wiring on an upper layer on the substrate.
According to the present invention, one end of one of the paired electrically conductive regions forming the set of sub bit lines, is connected to the longitudinally opposite end of the other electrically conductive region by a wiring provided on an upper layer on the substrate. Preferably, one end on one side connected to the selection transistor of one of the paired two electrically conductive regions forming the set of sub bit lines is connected to the longitudinally opposite end of the other electrically conductive region by a wiring provided on an upper layer on the substrate.
According to the present invention, there are provided a plurality of electrically conductive regions extending parallel to one another on a substrate surface forming a memory cell region, two of the electrically conductive regions are connected as a pair to form a set of sub bit lines; the one set of the sub bit lines being connected to a main bit line via a selection transistor, a plurality of the selection transistors are arranged facing to one another on both longitudinal end sides of the memory cell array, the memory cell array is formed by a plurality of (M) sets, each set being composed of a plurality of (N) word lines, and the pairs of electrically conductive regions each forming the set of sub bit lines being M sets of electrically conductive regions in keeping with the M sets forming the memory cell array. For each of the M sets of paired electrically conductive regions, the end on one longitudinal end side of one of the paired electrically conductive regions and the end on the other longitudinal end side of the other of the paired electrically conductive regions are interconnected via a wiring on an upper layer on the substrate. The paired electrically conductive regions of each of the M sets are connected common to one of the selection transistors via the wiring on an upper layer on the substrate.
The present inventors have recognized that when the structure of the U-shaped electrically conductive regions is applied to for example a programmable non-volatile semiconductor storage device, it is necessary to take suitable measures such as decreasing the write current. Another aspect-related method of the present invention is a method for controlling the writing in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting a pair of electrically conductive regions extending parallel to each other on a substrate surface, a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array, and in which a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged in an interchanged fashion. The method comprises applying a ground potential to a first one of two neighboring electrically conductive regions associated with a selected memory cell, a preset positive voltage to a gate electrode associated with the selected memory cell and for applying, when writing in the memory cell, a voltage intermediate the positive voltage applied to the second electrically conductive region and the ground potential to a third electrically conductive region neighboring to the second electrically conductive region to which the positive voltage is applied, the third electrically conductive region lying on the opposite side to the second electrically conductive region to which the positive voltage is applied.
In the write controlling method according to the present invention, there are applied a ground potential to a first one of two neighboring electrically conductive regions associated with a selected memory cell, a preset positive voltage to a gate electrode associated with the selected memory cell and, when writing in the memory cell, a voltage of the same level as the second electrically conductive region to a third electrically conductive region neighboring to the second electrically conductive region to which the positive voltage is applied, the third electrically conductive region lying on the opposite side to the first electrically conductive region. There is also applied a ground potential to a first one of two electrically conductive regions associated with a selected memory cell, a preset positive voltage to a gate electrode associated with the selected memory cell and for applying, when writing in the memory cell, a positive voltage of the same level as that of the second electrically conductive region, to an electrically conductive region neighboring to the second electrically conductive region supplied with the positive voltage, and to an electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region, the electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region being from the electrically conductive regions neighboring to a third by being electrically conductive region forming a set of the sub bit lines by paired to the second electrically conductive region. There is also applied a voltage intermediate the positive voltage supplied with the positive voltage and the ground voltage to at least one of the first electrically conductive region and an electrically conductive region arranged between a fourth electrically conductive region forming a set of sub bit lines by being paired with the first electrically conductive region and the electrically conductive region to which is applied the positive voltage.
In accordance with another aspect of the present invention, there is provided a method of controlling read operation in a semiconductor storage device in which a set of sub bit lines are formed by interconnecting a pair of electrically conductive regions extending parallel to each other on a substrate surface, a plurality of selection transistors for connecting a set of sub bit lines to an associated main bit line are arranged on both longitudinal end sides of a memory cell array, and in which a plurality of sets of sub bit lines respectively connected to the selection transistors arranged on one and on the other longitudinal end sides of the memory cell array are arranged in an interchanged fashion. The method comprises applying a ground potential to a first one of two neighboring electrically conductive regions associated with a selected memory cell, a preset positive voltage to a gate electrode associated with the selected memory cell and for applying, when writing in the memory cell, a voltage of the same level as the second electrically conductive region to a third electrically conductive region neighboring to the second electrically conductive region to which the positive voltage is applied, the third electrically conductive region lying on the opposite side to the first electrically conductive region.
In accordance with another aspect of the present invention, a method of controlling read operation in a semiconductor storage device comprises applying a ground potential to a first one of two neighboring electrically conductive regions associated with a selected memory cell, a preset positive voltage to the second electrically conductive region and a preset positive voltage to a gate electrode associated with the selected memory cell, and for applying, when reading out from the memory cell, a positive voltage of the same level as that of the second electrically conductive region, to an electrically conductive region neighboring to the second electrically conductive region supplied with the positive voltage, and to an electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region, the electrically conductive region forming sub bit lines having an electrically conductive region other than the first electrically conductive region being from the electrically conductive regions neighboring to a third by being electrically conductive region forming a set of the sub bit lines by paired to the second electrically conductive region, and applying a ground voltage to at least one of the first electrically conductive region and an electrically conductive region arranged between a fourth electrically conductive region forming a set of sub bit lines by being paired with the first electrically conductive region and the electrically conductive region to which is applied the positive voltage.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.